1. Field of the Invention
The present invention relates to data transfer between buses of a computer system. More particularly, the present invention relates to a direct memory access (DMA) transfer control apparatus for transferring data between devices, a bus adaptor for transferring data between buses, a computer system incorporating either or both of the bus adaptor and the DMA transfer control apparatus, and a method for transferring data between buses.
2. Description of the Related Art
Conventionally, a DMA transfer method for directly transferring data between transfer devices without a CPU is widely known and, for example, is used to perform direct data transfer between memories.
In DMA transfer, information required for transfer, such a data transfer source address, a data transfer destination address, a data transfer size or the like, is set in registers or the like of a DMA transfer control apparatus, and thereafter, a transfer operation is executed by a CPU or the like controlling the start of transfer. Since the CPU is not required to perform a transfer control during transfer, data transfer can be performed at a higher rate than when data is transferred via the CPU, and in addition, the load on the CPU can be reduced. After data has been transferred in an amount corresponding to the transfer size set in the registers or the like, a DMA transfer end interrupt is asserted, depending on a setting of the DMA transfer control apparatus. The CPU, when detecting the DMA transfer end interrupt, reads the registers or the like of the DMA transfer control apparatus to monitor a result or a status of DMA transfer.
Also, in DMA transfer, burst transfer is often utilized in which, after only one address is designated, a plurality of pieces of byte data can be successively transferred.
In DMA transfer, when data transfer source address and data transfer destination address are set to have different byte alignments where the addresses are located, read data cannot be directly used as write data. Therefore, for example, a process of regenerating write data from two cycles of read data is required, depending on the addresses.
To solve such a problem, a conventional transfer control apparatus comprises a shifter for shifting read data and an accumulator for selectively accumulating shifted bytes and supplying output bytes (see U.S. Pat. No. 6,330,631).
A burst transfer operation in this conventional technique when transfer source addresses and transfer destination addresses have different byte alignments will be described with reference to FIG. 22. One piece of read data is subjected to a two-phase transfer process. In the first phase, read data is shifted, depending on a set address, and for a byte which can be immediately output as write data, a byte enable signal to be supplied to the accumulator is activated and the byte is written into the accumulator, and at the same time, the accumulator outputs write data. In the second phase, for a byte which was not output as write data in the first phase, a byte enable signal to be supplied to the accumulator is activated and the byte is written into the accumulator, and resultant data is accumulated. These bytes are output as write data together with a portion of the next read data in the next first phase.
However, in the conventional transfer control apparatus, when transfer source addresses and transfer destination addresses have different byte alignments, a two-phase process is required for one piece of read data, resulting in a decrease in data transfer rate.